View SDA9188-3X_35255.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Picture-in-Picture Processor with On-Chip PLL
SDA 9188-3X
Preliminary Data
MOS IC
Features
q On-chip PLL q Full frame display for 50/60 Hz in order to increase the
vertical resolution and to suppress moving artifacts.
q Compatibility to the 16:9 display format by means of
q
q q q q q
independent setting of the vertical and horizontal decimation factors and the width of the border frame Decimation of the Y, U, V data for pictures sizes 1/9 and 1/16 with 6 bits width of the input word without P-DSO-28-3 rounding error Intermediate storage of the inset picture (on-chip-memory) RGB- or Y-, U-, V-signal generation 100% pin- and software compatible with SDA 9188X if external PLL is used Increased bandwith of analog outputs due to higher output currents New select function for multi-PIP feature
Type SDA 9188-3X Functional Description
Ordering Code Q67100-H5142
Package P-DSO-28-3 (350 mil) (SMD)
The SDA 9188-3X Picture-in-Picture (PIP) processor with on-chip PLL combines two asynchronous picture sources so that a small moving picture (the inset picture) can be superimposed in a moving picture of normal size (the parent picture). The components of the video signal of the inset source have to be fed in a digitized form to the SDA 9188-3X (figure 1). Amplitude resolution of the signal components is 6 bit at a sampling rate of 13.5 MHz for the luminance signal and 3.375 MHz for the chrominance signals.
Semiconductor Group
1
08.93
SDA 9188-3X
The PIP processor SDA 9188-3X handles picture reduction (decimation with horizontally and vertically acting filters), intermediate data storage in an integrated image memory (169.812 bits) as well as the output of the decimated picture. The picture can be set 1/9 or 1/16 of its original size. In order to indicate the border between parent picture and inset picture the inset picture can be surrounded with a frame: its width is adjustable in 2 stages and its brightness in 16 stages. Different signal sources can be identified by using different framing colors. The four corners of the parent picture are possible positions for the inset picture. The inset picture can also be inserted as a still picture, independently of the parent picture. The output signals of the SDA 9188-3X are analog. Either RGB or Y, U, V signals can be output, whereby a 6-bit broadband conversion is obtained for all components. Clamping for RGB output signal is performed in an RGB processor (e.g. TDA 4685). Only a few additional devices are required for a complete picture-in-picture system. Application circuits 1a and 1b illustrate the use of the PIP device. If the CVBS input signal is to be decoded using an analog color decoder for the PIP, the analog/ digital interface for the inset picture (3 A/D Converter, SDA 9187-2X) performs the conversion of the Y, U, V components into digital signals as well as the generation of the inset clocks BLNI and LL3I. The SDA 9188-3X processes both 50 Hz/625 and 60 Hz/525 line signals. The field frequency can be 50/60 Hz or 100/120 Hz. For systems with Siemens Dig TV Featurebox a field frequency of 100 Hz or 120 Hz is also possible by doubling the clock frequency LL3P (LL1.5P). Frame mode display with 50 Hz or 60 Hz can also be set via the I2C bus. Adaptation to the number of lines occurs automatically. If the field frequency in the parent and inset channels are different, artifacts may result in the picture. Synchronization with the parent channel is performed via the horizontal and vertical sync signals HSP/SAND and VSP. The clock fequency is 13.5 MHz (LL3P) without standard conversion and 27 MHz (LL1.5P) with standard conversion (100/120 Hz). The display clock is generated on chip. Optionally the external clock generator SDA 9086-3 can be used in the same way as with the SDA 9188X. The horizontal and vertical sync signals BLNI and VSI plus the LL3I clock (13.5 MHz) are used for synchronization with the inset source. The interface between inset and parent channel is done by the on-chip memory. The memory write access is controlled by the inset clock and the read access is controlled by the parent clock. The SELECT output signal inserts the inset picture into the parent picture driving an external analog switch, e.g. the TDA 4685. All operation modes of the SDA 9188-3X can be controlled via the I2C bus. Nine registers can be used.
Semiconductor Group
2
SDA 9188-3X
Pin Configuration (top view)
Semiconductor Group
3
SDA 9188-3X
Pin Definitions and Functions Pin No. 1 2 3 4 Symbol BLNI VSI Function Blanking inset Vertical synchronous inset Analog supply Reference voltage Descriptions Inset line synchronization Inset field synchronization
VDD A VREF
VDD-power supply for D/A converter and PLL
External resistor can be used for generation of the internal reference voltage
5-7 8 9 10 11 12 13 14 15 16 17 18-27 28
OUT1-OUT3
Analog R, G, B, Y, -U, -V- Analog RGB or YUV outputs outputs Analog ground SELECT Horizontal synchronous/ Sandcastle parent Vertical synchronous parent Line locked clock parent/ Output of the oscillator Input of the oscillator Digital ground Serial Data Serial Clock Line locked clock inset UV, Y-Data Digital supply Ground for D/A converter and PLL Valid signals at OUT1-OUT3 Parent line synchronization Parent field synchronization Parent system clock or to be connected to the crystal To be connected to the crystal Ground I2C Data I2C Clock Inset system clock Digital YUV input data
VSS A
SELECT HSP/SAND VSP LL3P/QX1 QX2
VSS
SDA SCL LL3I UV0-UV3, Y0-Y5
VDD
VDD supply
Semiconductor Group
4
SDA 9188-3X
Block Diagram Semiconductor Group 5
SDA 9188-3X
Circuit Description Data Transfer The digital data are transferred under the control of LL3I, BLNI and VSI on pins YS0-YS5 and UVS0-UVS3. The decimated data are stored automatically. Either R, G, B, or Y, -U, -V analog signals are available at the outputs OUT1-OUT3. The validity of the signals is identified by SELECT = 1. In a digital system environment the input is controlled by LL3P, HSP and VSP. Inset Data Reduction The data rate at the inputs YS0-YS5, UVS0-UVS3 is 13.5 MHz in multiplexed format, see figure 1. In order to reduce the quantity of data which have to be stored and to prevent artifacts in the inset picture, nine pixels are processed into one inset pixel for a 1/9 picture. For the 1/16 picture 16 pixels are processed into one inset pixel. This is done by horizontal and vertical averaging of pixels: The characteristic of decimation for the luminance signal is 1-1-1 for 1/9- and 1-1-1-1 for 1/16 picture. Crominance signal: 1-2-1 for 1/9 and 1-1-1-1 for 1/16 picture.
Figure 1 Input Data Format
Semiconductor Group
6
SDA 9188-3X
During the decimation process the following parts of the original picture are processed: 1. DECHOR/DECVER = 0(1/9-Picture) during 625 line mode: during 525 line mode: SIZE = 1(1/16-Picture): during 625 line mode: during 525 line mode: Line 36 ... 302; Pixel 13 ... 636 Line 26 ... 256; Pixel 13 ... 636 Line 36 ... 303; Pixel 17 ... 640 Line 26 ... 257; Pixel 17 ... 640
2.
Temporary Storage of Inset Picture The PIP memory has a capacity of 169.812 bits. The memory organisation is 89 x 212 x 9 bits. Data are written in with the inset and read out with the parent clock frequency. For standard video signals with 50 or 60 Hz a full frame display is possible. To assure a correct display of the two fields, the control of the memory is done dependendly of the field and the phase relation of the Inset and Parent channel. Frame mode display is only possible for standard 50 Hz/ 60 Hz video signals. Certain VCR-functions (e.g. fast forward-mode), non interlaced signals and 50 Hz/60 Hz mixed-mode would cause inacceptable picture distortions. Under these conditions the SDA 9188-3X switches automatically into field mode display. Also freezed pictures can only be displayed in the field-mode. Output of Data in Parent Window The four corners of the parent picture are foreseen as positions for inserting the inset picture. To enable compatibility to different system configurations, readout from memory can be shifted horizontally in 63 steps by max. 252 LL3P cycles and vertically in 15 steps by max. 30 lines in the parent field setting the control bits RDH and RDV in control register 2 and 3. The coordinates BRP, BRL of the normal location of all four insertion positions are given in table 3 for RDH = RDV = 8. The SELECT signal goes high during the display of the inset picture. Outside of the inset picture SELECT signal is low and the analog outputs OUT1-OUT3 provide the black level. The external wiring can produce a delay between the SELECT signal and the analog outputs. This delay can be compensated by bits SD0-SD2 in register 2 via the I2C bus. A frame with one of eight colors can be inserted using control bits FRON, COL0-2. The width of the frame is fixed by FRWV at three or two lines and by FRWH at six or four pixels. The brightness can be adjusted in 16 stages.
Semiconductor Group
7
SDA 9188-3X
Figure 2 Insertion Positions of Inset Picture
Table 3 Display of Inset Picture Position TV Standard (Parent) (Frame Line Number) Picture Size Location of Top Left Corner Point for FRWH = 1, FRWV = 1 TV Line (FL) NINT 0 0 1 1 1 1 2 2 2 2 625 525 625 525 625 525 625 525 * 625 525 * X X 1/9 1/9 1/16 1/16 1/9 1/9 1/16 1/16 57 41 57 41 57 41 365 293 409 333 INT 29 21 29 21 29 21 183 147 205 167 54 54 448 448 502 502 54 54 54 54 Pixel (FP)
Semiconductor Group
8
SDA 9188-3X
Position TV Standard (Parent) (Frame Line Number)
Picture Size
Location of Top Left Corner Point for FRWH = 1, FRWV = 1 TV Line (FL) NINT INT 183 147 205 167 448 448 502 502 Pixel (FP)
3 3 3 3
625 525 * 625 525 *
1/9 1/9 1/16 1/16
365 293 409 333
Pixel data related to positive HSP edge Line data related to positive VSP edge * If the System is in the 50/60 Hz mixed mode RDV in Register 2 is forced to the logical "0" state. If FRWV is set to "0" during the INT Mode the inset position will be shifted by one line. The width of the borderframe is depending on the programming of the bits FRWV and FRWH (in Register 5) 3 or 2 lines and 6 or 4 pixels. The pixels and line number of the inset picture depend on the standard of the inset channel and on the selected picture size.
Table 1 Inset Picture Size Picture Size 1/9 1/9 1/16 1/16 TV Standard (Inset) (Frame Line Number) 625 525 625 525 Pixel Number P Y 212 212 160 160 U 53 53 40 40 V 53 53 40 40 88 76 66 57 Line Number L
Interpolation of Chrominance Data Rate to Luminance Data Rate To avoid chrominance artifacts after D/A conversion and for digital RGB conversion, the data rate of the chrominance signals is quadrupled in order to match the luminance data rate. This is done by repeating the chrominance data twice followed by low-pass filtering.
Semiconductor Group
9
SDA 9188-3X
RGB, Y, U, V Outputs A digital RGB matrix converts the Y, U, V data in R, G, B data. The equation of the implemented RGB Matrix are: R = Y + 0.75 V G = Y - 0.375 V - 0.1875 U B=Y+U For a signal with 100 % white and 75 % color saturation the amplitudes of the analog input signals have to be set according the following relation: Y / U / V = 0.72 / 0.95 / 1 By means of an internal switch at the output of the RGB matrix it is possible to by-pass the matrix with the digital data for Y, U and V and feed them directly into the D/A converters. During this operation mode the chrominance data U and V will be inverted. D/A Conversion SDA 9188-3X includes three 6-bits D/A converters. Each D/A converter delivers a current through an external resistor that is to be connected between OUT1-OUT3 and VSSA. The resistor value determines the output voltages (see application circuit). The assignment of outputs OUT1-OUT3 to R, G, B and Y, U, V is shown in table 5. It is possible to change the output voltage via I2C bus Register 4. The tolerances of the output voltages can be reduced significantly if the resistor at VREF is replaced by means of a constant current source.
Table 5 Assignment of Output Signals to OUT1-OUT3 Output OUT1 OUT2 OUT3 RGB R G B YUV -V Y -U
Borderframe The width of the border frame can be adjusted in two steps, the intensity of the frame can be set in 16 steps via the I2C bus.
Semiconductor Group
10
SDA 9188-3X
I2C BUS Organization of I2C Bus Registers SDA 9188-3X has the device address 00101110 = 2EH Applying the supply voltage VDD produces a power-up reset. The bus lines SDA and SCL are enabled. All bits in the registers except bit PL27 (D3 in Register 0) are set to 0. Bit PL27 is set to 1. The I2C bus interface works as a slave receiver and only functions if the inset clock LL3I is available. Write Operation S 0010 1110 A
0000
XXXX
A
XXXX
XXXX
A
P
Start
write Write
Ack
Stop
Chip address byte
Register address
Data word1
After writing a byte into any register, the register address is automatically incremented for the write access to the next register. The following table shows the functions that can be set on the I2C bus and define the data bytes. Not used data bits have to be written with "0" . Before PON = 1 all other bits have to be defined in relation to the used hardware. Function
CONTROL 0 CONTROL 1 CONTROL 2 CONTROL 3 CONTROL 4 CONTROL 5 CONTROL 6 CONTROL 7 CONTROL 8 CONTROL 9
SUBaddress
00 01 02 03 04 05 06 07 08 09
D7
0 0 0 POS 1 CON0 DECVER FRAME AMSEC 0 0
D6
0 0 SD2 POS 0 CON1 DECHOR STATI STATP 0 PLLTC
D5
STILL 0 SD1 RDH 5 CON2 FRWV VSIIS VSPIS 0 SOS
D4
SIZE FRY SD0 RDH 4 CON3 FRWH VSIDEL4
D3
PL27 COL2 RDV 3 RDH 3 0 PMOD1 VSIDEL3
D2
NINT COL1 RDV 2 RDH 2 SOP PMOD0 VSIDEL2
D1
OUT COL0 RDV 1 RDH 1 PLLOFF IMOD1 VSIDEL1
D0
PON FRON RDV 0 RDH 0 HSP5 IMOD0 VSIDEL0
VSPDEL4 VSPDEL3 VSPDEL2 VSPDEL1 VSPDEL0 FRYEN FRY5 FRY4 FRY3 FRY2 0
VCOSEL3 VCOSEL2 VCOSEL1 VCOSEL0
Table 6: I2C Bus Register The bits are numbered in the reverse order to the data stream of the I2C bus. If the control software addresses the internal register number 8 or 9 there is no longer any software compatibility to the devices SDA 9088-2 and SDA 9089X. This is caused by the fact that in these devices register 0 and 1 can also be accessed via the subaddress 08 and 09.
Semiconductor Group
11
SDA 9188-3X
Register 0 (Address 00H) Bit d0 d1 d2 d3 d4 d5 d6, d7 Function 0 = PIP OFF 1 = PIP ON 0 = Y, -U, -V 1 = RGB 0 = Normal picture 1 = Double scan 0 = 13.5 MHz PLL 1 = 27 MHz PLL 0 = 1/9 1 = 1/16 0 = normal picture 1 = still picture not assigned Name PON OUT NINT PL27 SIZE STILL Remarks If d0 = 0, no SELECT generated PON = 1 should be set after the initialization Output format Reproduction mode Switching of the clock prescaler of the PLL for 50/60 Hz or 100/120 Hz operation mode Picture size; if d4 = 0 the picture size depends on DECHOR, DECVER in Register 5 Still/moving picture
Register 1 (Address 01H) Bit d0 d1-d3 Function 0 = without frame 1 = with frame frame color d3 0 0 0 0 1 1 1 1 d4-d7 d2 0 0 1 1 0 0 1 1 d1 0 1 0 1 0 1 0 1 Name FRON COL0COL2 = = = = = = = = blue violet green white red yellow orange cyan FRY Only valid if FRYEN = 0 Remarks FRON
Intensity of the border frame 1 = dark frame for white, yellow,orange and cyan bright frame for blue, violet, green and red 0 = bright frame for white,yellow, orange and cyan dark frame for blue, violet, green and red
d7-d5
without function
Semiconductor Group
12
SDA 9188-3X
Register 2 (Address 02H) Bit d0-d3 Function Vertical read delay in HSP period d3 0 0 0 1 1 1 d4-d6 d2 0 0 0 1 1 1 d1 0 0 1 : 0 1 1 d0 0 =0 1 =2 0 =4 1 0 1 = 26 = 28 = 30 SD0SD2 Name RDV0RDV3 Remarks Increment in two HSP periods. If POS1 = 1 is selected, i.e. 525-lines parent picture and 625-lines inset picture are displayed, then RDV bits are not evaluated.
SELECT delay in LL3P period d6 0 0 0 0 1 1 1 1 d5 0 0 1 1 0 0 1 1 d4 0 1 0 1 0 1 0 1
= = = = = = = =
0 1 2 3 4 5 6 7
d7
without function
Semiconductor Group
13
SDA 9188-3X
Register 3 (Address 03H) Bit d0-d5 Function Horizontal read delay in LL3P period d5 0 0 0 1 1 1 d6, d7 d4 0 0 0 1 1 1 d3 0 0 0 : 1 1 1 d2 0 0 0 1 1 1 d1 0 0 1 0 1 1 d0 0 =0 1 =4 0 =8 1 0 1 = 244 = 248 = 252 POS0POS1 Name RDH0RDH5 Remarks Increment in four LL3P periods
Inset picture location d7 0 0 1 1 d6 0 1 0 1
top left top right down left down right
Semiconductor Group
14
SDA 9188-3X
Register 4 (Address 04H) Bit d0 d1 d2 d3 d4-d7 Contrast DA-Converter CON 0-3 Function 1 = TTL level at HSP 0 = Internal PLL 1 = External PLL 0 = SELECT PULLUP INTERN 1 = SELECT PULLUP EXTERN Name HSP5 PLLOFF SOP Remarks Set to `1' Switching between internal and external clock generation Open Drain for SELECT output Without function, has to be set to 0 with an external resistor of 10 k between VSS and VREF the output level for (d7 ... d4) = 0001 is nearly the same as for 3.9 k and (d7 ... d4) = 0000 Contrast minimal
d7 0 1 0 1
d6 0 0 0 1
s
d5 0 0 0 0
d4 0 0 0 0
s
s
1
1
1
1
Contrast maximal
Semiconductor Group
15
SDA 9188-3X
Register 5 (Address 05H) Bit d1, d0 Function Name Remarks For multistandard applicat. Fixed setting Fixed setting Undisturbed switching during the change of the received station
00 = Automatic TV standard recognition IMOD0, 1 01 = 50 Hz 10 = 60 Hz 11 = Freeze the current mode
d3, d2
same like d1, d0
PMOD0, 1 as above but for the parent channel FRWH Separated setting of the frame width and height is possible i.e. for 16:9 operation Separated setting of the frame width and height is possible i.e. for 16:9 operation Separated setting of the picture width and height is possible i.e. for 16:9 operation, but only if Size = 0 in Register 0 Separated setting of the picture width and height is possible i.e. for 16:9 operation, but only if Size = 0 in Register 0
d4 0 = Frame width horizontal: 6 Pixel 1 = Frame width horizontal: 4 Pixel d5 0 = Frame width vertical: 3 lines 1 = Frame width vertical: 2 lines
FRWV
d6 0 = Horizontal decimation 3:1 1 = Horizontal decimation 4:1
DECHOR
d7 0 = Vertical decimation 3:1 1 = Vertical decimation 4:1
DECVER
Semiconductor Group
16
SDA 9188-3X
Register 6 (Address 06H) Bit d4:d0 Function Setting the delay of VSI (see test circuit 6) Name VSIDEL Remarks Setting is possible in steps of 2,37 s (see measurement circuit 6) Noise reduction of the VSI pulse (should be set to `1' under normal conditions.) If the check is active a full frame display is only possible if the number of lines is exactly according the TV standard: 312.5 (50 Hz) 262.5 (60 Hz) Only active if the line number and the interlace mode are equal for both inset and parent signal. If the display mode is 100/ 120 Hz or progressive scan d7 has to be set to 0
d5
0 = Vertical noise reduction inactive 1 = Vertical noise reduction active 0 = Check for correct TV standard inactive 1 = Check for correct TV standard active
VSIS
d6
STATI
d7
0 = Field display 1 = Frame display
FRAME
Semiconductor Group
17
SDA 9188-3X
Register 7 (Address 07H) Bit d4:d0 Function Delay of the VSP pulse Name VSPDEL Remarks Setting is possible in steps of 2,37 s (50 Hz or 1,185 s 100 Hz) (see measuring circuit 6) Noise reduction for the vertical pulse of the parent channel (should be set to `1' under normal conditions). If the check for the correct TV standard is active a full frame display is only possible if the number of lines is exactly according the TV standard: 312.5 (50 Hz) 262.5 (60 Hz) Doubling of the gain if a sufficient SECAM decoder without delay line is used
d5
0 = Vertical noise reduction OFF 1 = Vertical noise reduction ON
VSPIS
d6
0 = Check for correct TV standard inactive 1 = Check for correct TV standard active
STATP
d7
0 = PAL/NTSC 1 = SECAM
AMSEC
Register 8 (Address 08H) Bit d3:d0 Function 0000 = min. brightness of the border frame 1111 = max. brightness of the border frame 0 = brightness of the border frame can be selected by FRY 1 = brightness of the border frame can be selected by FRY5:2 d7:d5 not used to be set to "0". Name FRY5:2 Remarks Setting only valid if the bit d4 is set to `1'
d4
FRYEN
Semiconductor Group
18
SDA 9188-3X
Register 9 (Address 09H) Bit d0 d1 ... d4 Function - VCO Nominal Frequency Name Remarks Set to `0' VCOSEL Set to `0' under nominal 0 ... 3 conditions SOS If d5 = 1 Pulldown-transistor of select output is switched OFF Resistor to ground required 0 = fast time constant 1 = slow time constant Set to `0'
d5
Select open Source
d6
PLL-Time constant
PLLTC
d7
-
Semiconductor Group
19
SDA 9188-3X
Absolute Maximum Ratings TA = 0 ... 70 C (all voltages are referred to VSS) Parameter Supply voltage Pin voltages Difference between Ambient temperature Storage temperature Power dissipation Thermal resistance Operating Range Symbol min. Limit Values max. 6 V V V C C W K/W -1 -1 - 0.25 - 20 - 20 Unit Test Condition
VDD VIN VDD/VDDA TA Tstg Ptot Rth SU
VDD + 0.5
0.25 70 125 1 55
TA = 0 ... 70 C
Supply voltage Ambient temperature
VDD TA
4.5 0
5.5 70
V C
Characteristics TA = 0 ... 70 C (all voltages are referred to VSS) Parameter Supply voltage Current consumption digital analog Symbol min. Limit Values typ. 5 40 10 max. 5.5 120 18 V mA mA without load LL3I = 13.5 MHz LL3P = 27 MHz 4.5 13 5 Unit Test Condition
VDD/VDDA IDD IDD A
Inputs YS0-YS5, UVS0-UVS3 LL3I, BLNI, VSI, LL3P, VSP H-input voltage L-input voltage Input capacitance Input leakage current (not valid for LL3P) Input leakage current
VIH VIL CI IL
LL3P/ QX2
2.3 - 1.0
VDD
0.8 7 10 200
V V pF A A
VIH = 5.5 V VIH = VDD
Semiconductor Group
20
SDA 9188-3X
Characteristics (cont'd) Parameter Symbol min. Output Select H-output voltage Limit Values typ. max. Unit Test Condition
VQH VQH
2.4 1.5 0
VDD VDD
0.4
V V V V V ns
L-output voltage H-output voltage L-output voltage Transition period
1) 2)
VQL VQH VQL tr, tf
VDD
0 1 15
- IQH = 0.2 mA, SOP = 0 - IQH = 4.5 mA,2) SOS = 1, SOP = 0 IQH = 1.6 mA SOP = 0, SOS = 0 SOP = 1 IQL = 5 mA 1) SOP = 1, SOS = 0 SOP = 0, SOS = 0 CI = 30 pF
Measuring Circuit 9a Measuring Circuit 9b
Input HSP / SAND H-input voltage L-input voltage Input capacitance Input leakage current
VIH VIL CI IL
2.3 - 1.0 - 10
VDD
0.8 7 10
V V pF A
HSP5 = 1 HSP5 = 1 0 V VDD + 0.5 V
Semiconductor Group
21
SDA 9188-3X
Characteristics (cont'd) Parameter Symbol Limit Values min. nom. max. Unit Test Condition Measuring Circuit
Input SCL, In/Output SDA L-input voltage H-input voltage Input leakage current Input capacitance Input frequency Transition period Max. capacitance at bus Fall time SDA by acknowledge
VIL VIH IL CI fSCL tr, tf Cmax tf VAL
-1 3
1.5
VDD
10 7 100 2 400 0.2 0.4
V V A pF kHz s pF s V
VIH = 5,5 V
0
from 3 V to 1 V IAL = 3 mA
Output OUT1 ... 3 * Output current Output voltage Range
IO VOH
- 1.61 - 1.79 - 1.97 mA 0 1.0 2 Vpp
Resolution Load resistance Output capacitance Coupling capacitance Reference current Time constant
IO quant RL CO CC IREF tconst
0
28.4 560
1000 7
- 0.3 - 0.5 -3
47 - 0.58 - 0.8 35 0.5 3
A pF nF mA ns LSB %
VDDA = 5 V Bits D4 ... D7 of Reg. 4 = 0000 IREF = nom. VDDA = 5 V
1 1 1 1 1 1 1 1
BW = 4.5 MHz 1 Range 0 ... 1 V Bit d1 of Reg. 0 = 1
Differential nonlinearity ** Maximum difference of output current at the RGB outputs for the same full modulation Change of the output IO currents by changing of bits CON 0-3 in Register 4 Reference resistance RREF
20
%
RREF = 10 k
2.7
3.9
4.7
k
Bits D4 ... D7 of Reg. 4 = 0000
* The nominal color saturation is achieved in RGB mode by an amplitude ratio of 0.72/0.95/1 for Y/U/V at the inputs. ** of D/A converter
Semiconductor Group
22
SDA 9188-3X
Internal PLL
Maximum frequency tolerance + 7 % (includes variation of horizontal-frequency and resonator tolerance). Attention: Voltage at pins QX1, QX2 must be below the limit values of absolute maximum ratings under all conditions. Minimum input amplitude at pin QX2 = 1 VPP. Maximum series resistor of quartz or ceramic resonator. Load capacitance at pin 12, 13 33 pF 22 pF 15 pF 10 pF RS 10 20 30 40 max. 16.72 kHz 33.47 kHz 34.375 kHz Conditions Quartz Frequency 20.48 MHz Bit d3 of Reg. 0 = 0 Bit d3 of Reg. 0 = 1 Bit d3 of Reg. 0 = 1 Quartz Frequency 21.09 MHz
Horizontal Frequency
min 14.53 29.06 30
Semiconductor Group
23
SDA 9188-3X
Timing Diagram 1
Parameter
Symbol min.
Limit Values typ. max.
Unit
LL3I Period time Rise time Fall time Low time High time TLL3 I 68 74
tr tf
TL TH 30 28
80 5 4
ns ns ns ns ns
Semiconductor Group
24
SDA 9188-3X
Timing Diagram 2
Parameter
Symbol min.
Limit Values typ. max.
Unit
LL3P Period time Rise time Fall time Low time High time TLL1.5 34 37
tr tf
TL TH 14 12
40 4 4
ns ns ns ns ns
Semiconductor Group
25
SDA 9188-3X
Timing Diagram 3
Parameter
Symbol min.
Limit Values typ. max.
Unit
BLNI Period time 625 lines Period time 525 lines High time Set-up time HSP Period time 625 lines Period time 525 lines High time Set-up time
tBLN tBLN tBLN H tSU
864 858 1 12
864 864
864 864 857
TLL3I TLL3I TLL3I ns
tHSP tHSP tHSP H tSU
864 858 4 12
864 864
864 864 854
TLL3P / TLL1.5P TLL3P / TLL1.5P TLL3P / TLL1.5P ns
Semiconductor Group
26
SDA 9188-3X
Timing Diagram 4
Parameter
Symbol min.
Limit Values typ. max.
Unit
VSI Period time 625 lines Period time 525 lines High time Set-up time VSP Period time 625 lines Period time 525 lines High time Set-up time
tVS tVS tVS H tSU
312.5 262.5 1 15
TBLNI TBLNI TLL3I ns
tVS tVS tVS H tSU
312.5 262.5 1 15
THSP THSP TLL3P ns
Full frame display is possible if the input signal is fully according the TV standard. The phase relation of the VSI/BLNI or the VSP/HSP signals has to be programmed in a way that the rising edge is neither close to the rising edge of the HS pulse nor in the middle of the TV line. (Test circuit 6).
Semiconductor Group
27
SDA 9188-3X
Timing Diagram 5
Parameter
Symbol min.
Limit Values max.
Unit
YS, UVS Set-up time Hold time
tSU tSH
15 5
ns ns
Timing Diagram 6: Allowed phase relation of the VSP/HSP or the VSI/BLNI pulse if the VSPDEL 0:4 or VSIDEL 0:4 = 00000. Semiconductor Group 28
SDA 9188-3X
Measuring Circuit 1 Wiring of D/A Converter Outputs
Measuring Circuit 2 a Wiring of SELECT Output Circuit, if register 4, bit d2 = 1 register 9, bit d5 = 0
Measuring Circuit 2 b Wiring of SELECT Output, if register 4, bit d2 = 0 register 9, bit d5 = 1
Semiconductor Group
29
SDA 9188-3X
Application Circuit 1a Semiconductor Group 30
SDA 9188-3X
Application Circuit 1b Semiconductor Group 31

▲Up To Search▲

Price & Availability of SDA9188-3X

	To Download SDA9188-3X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .